The H5TQ1G43BFR-xxC, H5TQ1G83BFR-xxC and H5TQ1G63BFR-xxC are a 1,073,741,824-bit CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. SK Hynix 1Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.


  • VDD=VDDQ=1.5V +/- 0.075V
  • Fully differential clock inputs (CK, /CK) operation
  • Differential Data Strobe (DQS, /DQS)
  • On chip DLL align DQ, DQS and /DQS transition with CK transition
  • DM masks write data-in at the both rising and falling  edges of the data strobe
  • All addresses and control inputs except data,  data strobes and data masks latched on the  rising edges of the clock
  • Programmable CAS latency 6, 7, 8, 9, 10 and (11) supported
  • Programmable additive latency 0, CL-1, and CL-2  supported
  • Programmable CAS Write latency (CWL) = 5, 6, 7, 8
  • Programmable burst length 4/8 with both nibble sequential and interleave mode
  • BL switch on the fly
  • 8banks
  • Average  Refresh  Cycle   ( Tcase  of  0  °C~ 95°C )                                                        
    - 7.8 µs at 0°C ~ 85 °C                                                                
    - 3.9 µs at 85°C ~ 95 °C
  • Auto Self Refresh supported
  • JEDEC standard 78ball FBGA(x4/x8), 96ball FBGA(x16)
  • Driver strength selected by EMRS
  • Dynamic On Die Termination supported
  • Asynchronous RESET pin supported
  • ZQ calibration supported
  • TDQS (Termination Data Strobe) supported (x8 only)
  • Write Levelization supported
  • On Die Thermal Sensor supported
  • 8 bit pre-fetch
  • This product is in compliance with the directive pertaining of RoHS.

Technical Data Sheet

Technical Data Sheet Technical Data Sheet의 Part Number, Rev., Update Date, Remark를 나타낸 표 입니다.
Part Number Rev. Update Date Remark
H5TQ1G63BFR 1.1 2010-07-14  

Simulation Model

Simulation Model Simulation Model의 Part Number, Rev., Update Date, Remark를 나타낸 표 입니다.
Part Number Rev. Update Date Remark
IBIS 1.5 2010-03-15  
Hspice 1.0 2009-04-24  

Device Operation

Device Operation Device Operation의 Part File Name, Update Date, Remark를 나타낸 표 입니다
Part Number Update Date Remark
DDR3_device_operation_timing_diagram.pdf 2010-03-04  


SpeedSpeed의 Part Number, Speed를 나타낸 표 입니다.
Part Number Speed
G7 1066 7-7-7
H9 1333 9-9-9
PB 1600 11-11-11