PRODUCTS

HY27US08561A

The SK Hynix HY27(U/S)S(08/16)561A series is a 32Mx8bit with spare 8Mbit capacity. The device is offered in 1.8V Vcc Power Supply and in 3.3V Vcc Power Supply.

Its NAND cell provides the most cost-effective solution for the solid state mass storage market.

The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased.

The device contains 2048 blocks, composed by 32 pages consisting in two NAND structures of 16 series connected Flash cells.

   A program operation allows to write the 512-byte page in typical 200us and an erase operation can be performed in typical 2ms on a 16K-byte(X8 device) block.

Data in the page mode can be read out at 50ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command input. This interface allows a reduced pin count and easy migration towards dif­ferent densities, without any rearrangement of footprint.

Commands, Data and Addresses are synchronously introduced using CE#, WE#, ALE and CLE input pin.

The on-chip Program/Erase Controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data.

The modifying can be locked using the WP# input pin.

The output pin RB# (open drain buffer) signals the status of the device during each operation.  In a system with mul­tiple memories the RB# pins can be connected all together to provide a global status signal.

Even the write-intensive systems can take advantage of the HY27(U/S)S(08/16)561A extended reliability of 100K pro­gram/erase cycles by providing ECC (Error Correcting Code) with real time mapping-out algorithm.

 

Optionally the chip could be offered with the CE# don’t care function. This option allows the direct download of the code from the NAND Flash memory device by a microcontroller, since the CE# transitions do not stop the read opera­tion.

 

The copy back function allows the optimization of defective blocks management: when a page program operation fails the data can be directly programmed in another page inside the same array section without the time consuming serial data insertion phase.

This device includes also extra features like OTP/Unique ID area, Block Lock mechanism, Automatic Read at Power Up, Read ID2 extension.

 

The SK Hynix HY27(U/S)S(08/16)561A series is available in 48 - TSOP1 12 x 20 mm , 48 - USOP1 12 x 17 mm, FBGA 9 x 11 mm.

Features

  • FEATURES SUMMARY 
    HIGH DENSITY NAND FLASH MEMORIES

    - Cost effective solutions for mass storage applications
  • NAND INTERFACE
    - x8 or x16 bus width.
    - Multiplexed Address/ Data
    - Pinout compatibility for all densities
  • SUPPLY VOLTAGE
    - 3.3V device: VCC = 2.7 to 3.6V     : HY27USXX561A
    - 1.8V device: VCC = 1.7 to 1.95V   : HY27SSXX561A
  • Memory Cell Array   
    = (512+ 16) Bytes x 32 Pages x 2,048 Blocks   
    = (256+8) Words x 32 pages x 2,048 Blocks
  • PAGE SIZE
    - x8 device  : (512 + 16 spare) Bytes :  HY27(U/S)S08561A
    - x16 device: (256 + 8 spare) Words : HY27(U/S)S16561A
  • BLOCK SIZE
    - x8 device: (16K + 512 spare) Bytes
    - x16 device: (8K + 256 spare) Words
  • PAGE READ / PROGRAM
    - Random access: 12us (max.)
    - Sequential access: 3.3V : 50ns (min.)
                                        1.8V : 60ns (min.)
    - Page program time: 200us (typ.)
  • COPY BACK PROGRAM MODE
    - Fast page copy without external buffering
  • FAST BLOCK ERASE
    - Block erase time: 2ms (Typ.)
  • STATUS REGISTER
  • ELECTRONIC SIGNATURE
    - Manufacturer Code
    - Device Code
  • CHIP ENABLE DON'T CARE OPTION
    - Simple interface with microcontroller
  • AUTOMATIC PAGE 0 READ AT POWER-UP OPTION
    - Boot from NAND support
    - Automatic Memory Download
  • SERIAL NUMBER OPTION
  • HARDWARE DATA PROTECTION
    - Program/Erase locked during Power transitions
  • DATA INTEGRITY
    - 100,000 Program/Erase cycles
    - 10 years Data Retention
  • PACKAGE
    - HY27(U/S)S(08/16)561A-T(P)
    : 48-Pin TSOP1 (12 x 20 x 1.2 mm)              
    - HY27(U/S)S(08/16)561A-T (Lead)             
    - HY27(U/S)S(08/16)561A-TP (Lead Free)

    - HY27(U/S)S(08/16)561A-S(P)
    : 48-Pin USOP1 (12 x 17 x 0.65 mm)              
    - HY27(U/S)S(08/16)561A-S (Lead)             
    - HY27(U/S)S(08/16)561A-SP (Lead Free)

    - HY27(U/S)S(08/16)561A-F(P)
    : 63-Ball FBGA (9 x 11 x 10 mm)              
    - HY27(U/S)S(08/16)561A-F (Lead)             
    - HY27(U/S)S(08/16)561A-FP (Lead Free)

Technical Data Sheet

Technical Data Sheet Technical Data Sheet의 Part Number, Rev., Update Date, Remark를 나타낸 표 입니다.
Part Number Rev. Update Date Remark
HY27US08561A 0.5 2006-06-20